PCIType2Info
Declaration
typedef struct {
ulong SocketRegistersBaseAddress;
uchar CapabilitiesPointer;
uchar reserved1;
ushort SecondaryStatus;
uchar PrimaryBus;
uchar SecondaryBus;
uchar SubordinateBus;
uchar SecondaryLatency;
struct {
ulong Base;
ulong Limit;
} Range[4];
uchar InterruptLine;
uchar InterruptPin;
ushort BridgeControl;
} PCIType2Info
Prototype In
pcilib.h
Description
Structure defining PCI to CardBus bridge (type 2) PCI configuration register layout. We use this in the PCIDeviceInfo union so we can describe all types of PCI configuration spaces with a single structure.
Members
SocketRegistersBaseAddress |
Base address for control registers |
CapabilitiesPointer |
CardBus bridge capabilities pointer |
reserved1 |
Reserved: not used for this device type |
SecondaryStatus |
Secondary status |
PrimaryBus |
Primary bus number bridge is connected to |
SecondaryBus |
Secondary bus bridge controls |
SubordinateBus |
Subordinate bus for bridge |
SecondaryLatency |
Secondary latency |
Range |
Array of four base/limit ranges |
InterruptLine |
Interrupt line assigned to this device |
InterruptPin |
Interrupt pin assigned to this device |
BridgeControl |
Bridge control register |
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