This list of DEC documentation and documentation references has been compiled by me, Chris Demetriou. It describes documents that I've found useful, or just found, while porting NetBSD to DEC's Alpha-based workstations (see the NetBSD/alpha web pages for more information about that port) and during other system hacking experiences. It is in no way meant to be be complete, and may not even be useful to you. However, I hope that it is. If you've additions, corrections, or comments, please send them to me, cgd@NetBSD.ORG.
The documents that are provided here in machine-usable form are undoubtedly copyright by Digital Equipment Corp., but I've been told that I can do whatever I want with them, including give out copies to the world. Note that many, if not all, of the documents presented here in PostScript form can be found one one of DEC's WWW servers. I provide them here for easy reference (because some of them are hard to find there), and so that when DEC decides to stop distributing them the public will still have access to them.
For documents which are available on-line in this archive, file information (such as file name, file size, and the last time the document was modified in the archive) are also included where possible. To download a document, select the file name link. A file's name is a good indication of the type of its contents; gzipped text files have names ending with .txt.gz, gzipped PostScript files have names ending with .ps.gz, etc.
Where possible, I've tried to keep both current and older revisions of documents on-line, so that users can more easily find changes in specifications and bugs in the old manuals which have been causing them problems. When a document is superseded by a newer version, there is usually a comment in the document's revision information entry pointing to the newer version.
The on-line version of Alpha Architecture Reference Manual (Second Edition). Does not OS-specific PALcode documentation or console interface documentation.
This is the authoritative reference on the new 64-bit RISC architecture of Digital Equipment Corporation. Written by the engineers who developed the Alpha specifications, this book contains complete descriptions of the common architecture required for all implementations and the interface required to support the OSF/1 and OpenVMS operating systems.
Revision information: Superseded by Alpha AXP Architecture Reference Manual (Second Edition).
My comments: Not very complete or accurate in some areas (PALcode switching, interrupt and machine check handling). Good (canonical) description of the instruction set.
This is the authoritative reference on the Alpha AXP 64-bit RISC architecture of Digital Equipment Corporation. Written by the engineers who developed the Alpha specifications, Alpha AXP Architecture Reference Manual, Second Edition, contains a complete description of the common architecture required of all implementations and describes the interfaces to support the OpenVMS, DEC OSF/1, and Windows NT Alpha operating systems.
Revision information: Supersedes Alpha Architecture Reference Manual (First Edition).
My comments: Much more complete and accurate than the first edition. A must-have for any low-level Alpha hacker.
This manual describes the assembly language supported by the DEC OSF/1 Alpha AXP compiler systems, its syntax rules, and how to write some assembly programs.
The DEC OSF/1 Calling Standard for AXP Systems defines the requirements, mechanisms, and conventions used in the DEC OSF/1 interface that support procedure calls for DEC OSF/1 on AXP systems.
This guide explains how to use the Privileged Architecture Library code (PALcode) to customize DECchip 21064, 21064A, 21066, and 21068 components to meet a variety of hardware and software application needs.
My comments: Thin, but interesting. Details important-to-know facts about handling machine-checks (using the MCES IPR), and about switching PALcode.
This guide explains how to use the Privileged Architecture Library code (PALcode) to customize Alpha 21064, 21064A, 21066, 21066A, 21068, and 21164 microprocessor components to meet a variety of hardware and software application needs.
My comments: Looks like it might replace PALcode for Alpha AXP Microprocessors (EC-N0660-72).
This manual describes the behavior of the DEC 3000 AXP architecture as it pertains to writing system-level software, such as operating systems and drivers.
This manual describes the behavior of the 300, 300L, 300X, 300LX, 400, 400S, 500, 500S, 500X, 600, 600S, 700, 800, 800S, and 900 models.
Revision information: Updated March, 1994. Old revision didn't include the 3000/700 and 3000/900 models; not important, as they're apparently programatically the same as the 600 and 800 models, respectively.
My comments: This book tells the nitty gritty details about the DEC 3000 family: what hardware the machines have, where and how to talk to it, how the boot process works, what's in the PROMs, and so on. Of course, some information is unclear, some is missing, and there are bugs; life is tough for a system hacker. Mandatory if you're going to be writing an OS for or porting an OS to the DEC 3000 family.
This manual gives hardware information for the PB22H-KB System Module.
Revision information: Final Draft.
My comments: This manual covers the Alpha-based EISA-bus system also known as the Jensen, DECpc AXP 150, DEC 2000/300, KN121, and PB22H-KB. This manual appears to provide the essential programming information for the DECpc AXP systems, including a description of the on-board devices, I/O addresses, and interrupt control system. A must-have if you're porting an OS to or writing an OS for the DECpc AXP systems.
This manual describes the hardware of the PCI I/O subsystem in AlphaServer 8200 and 8400 systems. It discusses the operations of the DWLPA and DWLPB PCI adapters, and provides detailed information on the subsystem registers. The manual is intended for technical professionals such as operating system programmers and customer service engineers.
This document is a supplement to the AlphaServer 8200/8400 System Technical Manual (EK-T8030-TM). It discusses the specific features of the 4-Gbyte MS7CC-GA memory module. A maximum of sevel MS7CC-GA memory modules can be configured in a system, offering a total memory capacity of 28 gigabytes.
The Digital AlphaServer 8200 and 8400 systems are designed around the DECchip 21164 CPU. The TLSB is the system bus that supports nine nodes in the 8400 system and five nodes in the 8200 system. The AlphaServer 8400 can be configured with up to six single or dual processor CPU modules (KN7CC), seven memory modules (MS7CC), and three I/O modules (KFTHA and KFTIA). One slot is dedicated to I/O and is normally occupied by the integrated I/O module (KFTIA) that supports PCI bus, XMI, and Futurebus+ adapters. All other nodes can be interchangeably configured for CPU or memory modules. The AlphaServer 8200 can be configured with up to three CPU modules, three memory modules, and three I/O modules.
Revision information: This document is supplemented by AlphaServer 8200/8400 System Technical Manual Supplement: Memory (EK-MS7CC-TS) and AlphaServer 8200/8400 System Technical Manual Supplement: CPU (EK-T8030-TS).
The KN7CE CPU is based on a 440 MHz enhanced version of the Alpha 21164 microprocessor. Design changes on the KN7CE enable it to support Memory Channel and deliver higher performance. The AlphaServer 8200/8400 System Technical Manual (EK-T8030-TM) provides a full description of the CPU module. This document highlights the differences between the KN7CE and its two predecessors, and supplements the information in the AlphaServer 8200/8400 System Technical Manual.
This guide supplies reference, configuration, and installation information for the Digital AXPpci 33 Alpha PC motherboard.
This guide describes how to troubleshoot and service the Multia MultiClient Desktop. The guide covers Alpha- and Intel-based models.
This information is intended for VARs (value-added resellers), ISVs, and other system users or service providers who are configuring their own systems or adding features to existing AlphaStation 200/400 Series systems.
Revision information: April 1995.
The purpose of this manual is to provide programming information that will assist system programmers in writing AlphaStation 600 System support code for their operating system.
Revision information: July 1995. This is a new manual.
This document describes the functional and physical characteristics of the Sable System (AlphaServer 2100) CPU module. The Sable System is an implementation of the Digital Alpha AXP Architecture and uses the DECchip 21064 and DECchip 21064-A275 processor chips.
Revision information: Revision 1.1 - 5 August 1994
This document describes the Sable (AlphaServer 2100) I/O internal subsystem modules. This includes the Motherboard module, which is also the backplane of the Sable system, the Standard I/O module, and the Remote I/O module. All three modules are required for all Sable systems.
Revision information: Revision 1.3
This application note provides information necessary to program the Ethernet address ROM.
Revision information: Preliminary.
This application note provides information for design engineers who conduct Level 3 SPICE simulations of Alpha AXP microprocessors and peripheral chips.
Revision information: This document is superseded by EC-QA4XB-TE, which is in turn superseded by EC-QA4XC-TE.
This application note provides pin-to-model reference tables for Alpha microprocessors and peripheral chips. This application note is for design engineers who conduct Level 3 SPICE simulations of Alpha microprocessors and peripheral chips.
Revision information: This document supersedes EC-QA4XB-TE, which in turn supersedes EC-QA4XA-TE.
This information sheet provides answers about obtaining the DECchip 21040/DECchip 21041/DECchip 21140 unified device driver (DC21x4) executables and source.
Reference manual (programming information) for the DECchip 21030 PCI Graphics Accelerator.
My comments: Contains all of the necessary information for writing a device driver for 21030-based PCI video boards except for RAMDAC programming information.
Data sheet (pinouts, electrical and mechanical specifications) for the DECchip 21040 Ethernet LAN Controller for PCI.
Revision information: Preliminary; April 1994. This version supersedes the January 1994 version.
Revision information: April 1994. Superseded by DECchip 21040 PCI Ethernet LAN Controller Product Brief (EC-QH0PA-TE).
Reference manual (programming information) for the DECchip 21040 Ethernet LAN Controller.
My comments: Contains much of the necessary information for writing a device driver for the 21040-based PCI ethernet boards.
This application note provides information necessary to implement network connections to the DECchip 21040 Ethernet LAN controller. Connections can be made to CPUs with a direct connection to an onboard peripheral component interconnect (PCI) local bus, or to CPUs without a direct PCI connection by using a bus-to-bus interface.
Revision information: March 1995
Data sheet (pinouts, electrical and mechanical specifications) for the DECchip 21041 PCI Ethernet LAN Controller.
Revision information: Preliminary
Reference manual (programming information) for the DECchip 21041 PCI Ethernet LAN Controller.
Revision information: Preliminary
This document contains errata for the DECchip 21041 PCI Ethernet LAN Controller (revision DC1017-BA). It describes the following anomalies with this chip and offers workarounds to allow system designers and driver developers to use the DECchip 21041 successfully: Receive Watchdog Interrupt, Capture-Effect Algorithm, Auto-Negotiation Support, Underflow Reporting.
This application note provides information necessary to implement network connections to the 21041 Ethernet LAN controller. Connections can be made to CPUs with a direct connection to an onboard peripheral component interconnect (PCI) bus, or to CPUs without a direct PCI connection by using a bus-to-bus interface.
This application note provides information necessary to implement connections between the DECchip 21041 Ethernet LAN controller and boot ROM, serial ROM, and external register. It also describes a connection of several chips sharing one serial ROM and the format of the serial ROM programming.
This memo lists the 21041 features. It describes in detail each feature in terms of pinout, system configuration, and software interface.
Data sheet (pinouts, electrical and mechanical specifications, register descriptions) for the DECchip 21050 PCI-to-PCI Bridge.
Revision information: This document supersedes the DECchip 21050 PCI-to-PCI Bridge Data Sheet, EC-Q9XVA-TE.
Informs 21050 buyers that they probably need to upgrade their system BIOS.
This application note presents guidelines for hardware implementation of the DECchip 21050.
This application note presents guidelines for configuration of the DECchip 21050 in a system.
This document provides updated information for the ECchip 21050 PCI-to-PCI Bridge Data Sheet, EC-Q9XVA-TE.
Revision information: May 1995
Data sheet (pinouts, electrical and mechanical specifications, register descriptions) for the DECchip 21052 PCI-to-PCI Bridge.
This application note presents guidelines for hardware implementation of the DECchip 21052.
This application note presents guidelines for the configuration of the DECchip 21052 PCI-to-PCI Bridge in a system.
Informs 21052 buyers that they probably need to upgrade their system BIOS.
Details an interoperability problem between DECchip 21052 Revision B and Intel's Triton core logic chipset.
Data sheet (pinouts, electrical and mechanical specifications, register and instruction summaries) for the 233MHz and 275MHz versions of the DECchip 21064A Alpha AXP Microprocessor.
Revision information: Preliminary. This document is updated by DECchip 21064A-233, -275 Alpha AXP Microprocessor Data Sheet Update, EC-QDQVA-TE
Reference manual (pinouts, electrical and mechanical information, register and instruction descriptions) for the DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors.
Revision information: Preliminary. This document is updated by DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware Reference Manual Update, EC-QD2RA-TE
This document provides updated information for the DECchip 21064 and DECchip 61064A Alpha AXP Microprocessors Hardware Reference Manual, EC-Q9ZUA-TE.
This document provides updated information for the DECchip 21064-150, -166, -200 Alpha AXP Microprocessor Data Sheet, EB-N0136-72.
This document provides updated information for the DECchip 21064A-233, -275 Alpha AXP Microprocessor Data Sheet.
Data sheet (pinouts, electrical and mechanical specifications, register and instruction summaries) for the DECchip 21066 Alpha AXP Microprocessor.
Data sheet (pinouts, electrical and mechanical specifications, register and instruction summaries) for the DECchip 21068 Alpha AXP Microprocessor.
Reference manual (pinouts, electrical and mechanical information, register and instruction descriptions) for the Alpha 21066, 21066A, and 21068 Microprocessors.
Data sheet (pinouts, electrical and mechanical specifications, programming information) for the DECchip 21071 and DECchip 21072 Core Logic Chipsets.
Reference manual (programming information) for the DECchip 21130 PCI Integrated Graphics and Video Accelerator.
This application note provides important information about the DECchip 21130 video BIOS. BIOS and system engineers can use this application note to design the DECchip 21130 into a PC motherboard or PC add-in card.
This application note provides a list of EDO and non-EDO DRAM devices that have been tested and qualified for use with the DECchip 21130 Integrated Graphics/Video Accelerator. When the device is revised, all the parts listed will be retested and this document will be updated. As new DRAMs become available from suppliers, we will test them and issue new qualification reports. Graphics hardware and systems engineers can use this application note to design graphics controllers or motherboard-based graphics subsystems using the DECchip 21130.
Description of the 21140 Fast Ethernet LAN Controller for PCI.
This document describes how to implement system and network connections to the DECchip 21140 PCI Fast Ethernet LAN Controller.
Revision information: Preliminary.
Data sheet (pinouts, electrical and mechanical specifications) for the DECchip 21140 PCI Fast Ethernet LAN Controller.
Revision information: Preliminary.
This document provideds updated information for the DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual, EC-QC0CA-TE.
Reference manual (programming information) for the DECchip 21140 PCI Fast Ethernet LAN Controller.
Revision information: Preliminary. Supsersedes the DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual (EC-QC0CA-TE).
Revision information: October 1995. This document is superseded by Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller Product Brief, EC-QN7MB-TE.
Revision information: January 1996. This document supersedes DECchip 21140A PCI Fast Ethernet LAN Controller Product Brief, EC-QN7MA-TE.
Reference manual (programming information) for the DECchip 21140A PCI Fast Ethernet LAN Controller.
Revision information: Superseded by Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual, EC-QN7NC-TE.
Reference manual (programming information) for the Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller.
Revision information: Superseded by DECchip 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual, EC-QN7NB-TE.
Data sheet (pinouts, electrical and mechanical specifications) for the DECchip 21140A PCI Fast Ethernet LAN Controller.
Revision information: Superseded by Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller Data Sheet, EC-QN7PB-TE.
Data sheet (pinouts, electrical and mechanical specifications) for the Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller.
Revision information: Supersedes DECchip 21140A PCI Fast Ethernet LAN Controller Data Sheet, EC-QN7PA-TE.
Data sheet (pinouts, electrical and mechanical specifications) for the DECchip 21142 PCI Fast Ethernet LAN Controller.
Data sheet (pinouts, electrical and mechanical specifications, register and instruction summaries) for the Alpha 21164 Microprocessor.
Revision information: This document supersedes the Alpha 21164 Microprocessor Data Sheet EC-QAEPA-TE.
Hardware reference manual (function interfaces and programming information) for the Alpha 21164 Microprocessor.
21164 Microprocessor Pipe/Block Flow Diagram. This is a fold-out section in the printed version of Alpha 21164 Microprocessor Hardware Reference Manual (EC-QAEQB-TE).
This document is a support and reference document for using the Alpha 21164 microprocessor to design uniprocessor systems.
Revision information: This document is supserseded by DECchip 21171 Core Logic Chipset Technical Reference Manual (EC-QE18B-TE).
This document is a support and reference document for using the Alpha 21164 microprocessor to design uniprocessor systems.
Revision information: Preliminary. This document supersedes DECchip 21171 Core Logic Chipset Technical Reference Manual (EC-QE18A-TA).
This document describes how to configure and Alpha microprocessor evaluation board system and install Microsoft Windows NT Workstation 3.5 and Windows NT Server 3.5.
Revision information: Preliminary.
This application note describes the DECchip 21130 evaluation board (EB130) design. PCI graphics designers and manufacturers can use this note when designing with the DECchip 21130 PCI Integrated Graphics and Video Accelerator Chip.
This is the functional specification for the DECstation 3100/2100 desktop workstations.
This document is the functional specification of the DS5000/200 KN02 system module.
My comments: This table of contents for this document is in a separate file, DS5000/200 KN02 System Module Functional Specification (Revision 1.3) Table of Contents.
This document is the table of contents for the DS5000/200 KN02 System Module Functional Specification (Revision 1.3).
My comments: Figures 1-3 and 1-10 are in separate files.
Figure 1-3 from TURBOchannel Hardware Specification
Figure 1-10 from TURBOchannel Hardware Specification
This document defines the functional specification for the TURBOchannel Interface ASIC. The TcIA is a general purpose ASIC designed for use in TURBOchannel options modules.
This is the functional specification for PMAG-BA module.
This is the functional specification for the PMAD-AA Ethernet module.
This is the functional specification for the PMAZ-AA SCSI Module.
This handbook is a design guide for developers of Futurebus+ modules intended for use in Digital Equipment Corporation systems. Module designers, system integrators, Original Equipment Manufacturers, and end users of Digital products should find this handbook useful.
My comments: Note that some pages in the preface are out of order.
An article by Mark Woodbury of Digital Equipment Corporation, describing Futurebus+/VME64 Bridges.
My comments: This is the first part of a six-part document
My comments: This is the second part of a six-part document
My comments: This is the third part of a six-part document
My comments: This is the fourth part of a six-part document
My comments: This is the fifth part of a six-part document
My comments: This is the last part of a six-part document
This manual describes the SCSI/CAM Architecture interfaces. It also describes how to write device drivers for the SCSI/CAM implementation.
This guide defines Digital Equipment Corporation's implementation of the American National Standard for Information Systems--Small Computer System Interface-2 (SCSI-2) specification. It defines the mechanical, electrical, and functional requirements for interconnecting small computers and intelligent peripheral devices.
This guide is not intended to replace the SCSI-2 specification, but rather to specity which options of the SCSI-2 specification must be implemented, and to impose additional restrictions when necessary.